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HD49351BP/HBP
CDS/PGA & 10-bit A/D TG Converter
REJ03F0110-0100Z Rev.1.0 Jul 06, 2004
Description
The HD49351BP/HBP is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera digital signal processing systems together with a 10-bit A/D converter and timing generator in a single chip. HD49351 has deleted the stripe mode, pd_mix mode, and added the 5 - 6 pulse and H_msk2 - 4 as contrasted with HD49335. There are address map and timing generator charts besides this specification. May be contacted to our sales department if examining the details.
Functions
* * * * * * Correlated double sampling PGA 10-bit ADC Timing generator Operates using only the 3 V voltage Corresponds to switching mode of power consumption and operating frequency 220 mW (Typ), maximum frequency: 36 MHz (HD49351HBP) 150 mW (Typ), maximum frequency: 25 MHz (HD49351BP) * ADC direct input mode * FBGA 65-pin package
Features
* Suppresses low-frequency noise, which output from CCD by the correlated double sampling. * The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and registers. * High sensitivity is achieved due to the high S/N ratio and a wide dynamic range provided by a PG amplifier. * PGA, pulse timing, standby mode, etc., is achieved via a serial interface. * High precision is provided by a 10-bit-resolution A/D converter. * Difference encoded gray code can be selected as an A/D output code. It is effective in suppression of solarization (wave pattern). It is patented by Renesas. * Timing generator generates the all of pulse which are needed for CCD driving.
Rev.1.0, Jul 06, 2004, page 1 of 28
HD49351BP/HBP
Pin Arrangement
10 A B C D E F G H J K 9 8 7 6 5 4 3 2 1
32 31 30 29 26 24 22 XV3 XV2 XV1 DVdd3 H2 DVss4 H1
19 17 16 RG VD_i/o HD_i/o
33 34 28 27 25 23 21 20 18 15 XV4 CH1 DVdd4 1/4clk DVss4 1/2clk DVdd4 DVdd3 Reset CLK_in 35 36 CH2 CH3 38 37 XSUB CH4 40 39 SUB_PD SUB_SW 41 42 DVss3 Strob 43 45 Bias AVss 44 46 VRB ADC_in 14 14 13 DVss3 DVss3 DVdd2 12 D9 10 D7 9 D6 7 D4 5 D2 11 D8 8 D5 6 D3 4 D1 3 D0
48 49 52 55 56 57 59 61 62 2 VRM AVdd AVdd AVss test2 test1 DVdd1 41cont CDS_CS DVss1,2 47 50 51 53 54 58 60 63 64 VRT BLKC CDS_in BLKFB BLKSH DLLC MON Sdata SCK 1 ID
(Top view) Notes: 1. Pin 41 outputs the STROB, pin 39 outputs the SUB_SW when pin 61 is Low. 2. Pin 41 inputs the Vgate, pin 39 inputs the ADCK when pin 61 is High. 3. 1/2 and 4clk output terminal becomes 1/3 and 1/6clk output respectively, when operating TG in 3 divided mode.
Pin Description
BGA Pin No. K1 J1 H1 to D2 C1 C2, C3 B1 A1 A2 B2 A3 B3 B4 A4 B5 A5 B6 A6 B7 B8 A7 PAD No. 1 2 3 to 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Symbol ID DVss1, 2 D0 to D9 DVdd2 Dvss3 CLK_in HD_in VD_in Reset RG DVdd3 DVdd4 H1 1/2clk_o Dvss4 Dvss4 H2 1/4clk_o DVdd4 DVdd3 Description Odd/even number line detecting pulse output pin CDS Digital ground + ADC output buffer ground (0V) Digital output (D0; LSB, D9; MSB) ADC output buffer power supply (3 V) General ground for TG (0V) CLK input (max 72 MHz) HD input VD input Hardware reset (for DLL reset) Reset gate pulse output General power supply for TG (3V) H1,2 buffer power supply (3 V) H.CCD transfer pulse output-1 CLK_in 2 divided output. 3 divided output at 3 divided mode H1,2 buffer ground (0 V) H1,2 buffer ground (0 V) H.CCD transfer pulse output-2 CLK_in 4 divided output. 6 divided output at 3 divided mode H1,2 buffer power supply (3 V) General power supply for TG (3 V) I/O O -- O -- -- I I I I O -- -- O O -- -- O O -- -- Analog(A) or Digital(D) D D D D D D D D D D D D D D D D D D D D 30 mA/165 pF 2 mA/10 pF 30 mA/165 pF 2 mA/10 pF Schmitt trigger 3 mA/10 pF 2 mA/10 pF Remarks 2 mA/10 pF
Rev.1.0, Jul 06, 2004, page 2 of 28
HD49351BP/HBP
Pin Description (cont.)
BGA Pin No. A8 A9 A10 B10 B9 C10 C9 D9 D10 E9 E10 F9 F10 G9 H9 G10 H10 K10 J10 J9 K9 K8 J8 K7 K6 J7 J6 PAD No. 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Symbol XV1 XV2 XV3 XV4 CH1 CH2 CH3 CH4 XSUB SUB_SW SUB_PD STROB DVss3 AVss ADC_in BIAS VRB VRT VRM Avdd BLK_C CDS_in AVdd BLKFB BLKSH AVss Test2 Description V.CCD transfer pulse output-1 V.CCD transfer pulse output-2 V.CCD transfer pulse output-3 V.CCD transfer pulse output-4 Read out pulse output-1 Read out pulse output-2 Read out pulse output-3 Read out pulse output-4 Pulse output for electronic shutter SUB voltage control output-1. Input the ADCK when 61 pin is Hi SUB voltage control output-2 Flash control output. Input Vgate at Hi of 61pin General ground for TG (0 V) Analog ground (0 V) A/D converter input pin Bias standard resistance (33 k for Gnd) ADC bottom standard voltage (0.1 F for Gnd) ADC top standard voltage (0.1 F for Gnd) ADC middle standard voltage (0.1 F for Gnd) Analog power supply (3 V) Black level C pin (1000pF for Gnd) CDS input pin Analog power supply (3 V) Black level FB pin (1 F between BLKFB and BLKSH) Black level S/H pin Analog ground (0 V) H: Normal operation, L: CDS single operation mode Input 36; PBLK at testing, Input 37; OBP, Input 38; CPDM, Input 39; ADCLK, Input 40; SP2, Input 41; SP1 L: Slave mode, H: Master mode Analog delay DLL external C pin (100 pF for Gnd) Digital power supply (3 V) CDS, PAG, ADC part Pulse monitor (SP1, SP2, ADCLK, OBP, CPDM, PBLK output) Input STROB = pin 41, Input SUB_SW = pin 39 at Low Input Vgate = pin 41, Input ADCK = pin 39 at Hi Serial data CS at CDS part Input serial data Input serial clock I/O O O O O O O O O O I/O O I/O -- -- I -- -- -- -- -- -- I -- I O -- I Analog(A) or Digital(D) D D D D D D D D D D D D D A A A A A A A A A A A A A D Remarks 2 mA/10 pF 2 mA/10 pF 2 mA/10 pF 2 mA/10 pF 2 mA/10 pF 2 mA/10 pF 2 mA/10 pF 2 mA/10 pF 2 mA/10 pF 2 mA/10 pF 2 mA/10 pF 2 mA/10 pF
J5 K5 J4 K4 J3 J2 K3 K2
57 58 59 60 61 62 63 64
Test1 DLL_C Dvdd1 MON 41cont CDS_CS SDATA SCK
I O -- O I I I I
D A D D D D D D 2 mA/10 pF
Rev.1.0, Jul 06, 2004, page 3 of 28
HD49351BP/HBP
Input/Output Equivalent Circuit
Pin Name Digital output D0 to D9, RG, H1A to H2B, XV1 to XV4, CH1 to CH4, XSUB, SUB_SW, SUB_PD, STROB, MON ADCLK, OBP, CPDM, SP1,2, PBLK, CS, SCK, SDATA, CLK_in, HD_in, VD_in Equivalent Circuit
DIN STBY DVDD Digital input DVDD Digital output
Digital input
Analog
CDS_in
AVDD CDS_in
Internally connected to VRT
ADC_in
ADC_in
AVDD
Internally connected to VRM
BLKSH, BLKFB, BLKC
AVDD BLKFB
+ -
BLKSH BLKC
VRT, VRM, VRB
+ -
VRT
VRM
VRB
AVDD
+ -
BIAS
BIAS
AVDD
Rev.1.0, Jul 06, 2004, page 4 of 28
HD49351BP/HBP
Block Diagram
DVdd1 to 4 1/4clk_o 1/2clk_o
CLK_in
HD_in
VD_in
XSUB
AVdd
CH4
CH3
CH2
CH1
H2A
H1A
XV4
XV3
XV2
XV1
RG
SUB_SW SUB_PD STROB DLL
Timing generator
AVss DVss1 to 4 Reset
CPDM
OBP
ADCLK
ADC_in CDS_in BLKSH BLKC 10bit ADC
PBLK
SP2
SP1
D9 D8 CDS PGA D7 D6 D5 D4 D3 D2 D1 D0
BLKFB
DC offset compensation circuit
Serial interface
Bias generator
CDS_CS
SDATA
BIAS
SCK
VRT
Rev.1.0, Jul 06, 2004, page 5 of 28
DLL_C
MON
VRM
VRB
ID
Output latch circuit
HD49351BP/HBP
Internal Functions
Functional Description * CDS input CCD low-frequency noise is suppressed by CDS (correlated double sampling). The signal level is clamped at 14 LSB to 76 LSB (set by resister: 5 bit 2 LSB step controls) during the OB period. *1 Gain can be adjusted using 8 bits of register (0.132 dB steps) within the range from -2.36 dB to 31.40 dB. *2 * ADC input The center level of the input signal is clamped at 512 LSB (Typ). Gain can be adjusted using 8 bits of register (0.01784 times steps, register settings) within the range from 0.57 times (-4.86 dB) to 5.14 times (14.22 dB). *2 * Automatic offset calibration of PGA and ADC * DC offset compensation feedback for CCD and CDS * Pre-blanking Digital output is fixed at clamp level * Digital outputs enable function Note: 1. It is not covered by warranty when 14 LSB settings 2. Full-scale digital output is defined as 0 dB (one time) when 1 V is input. Operating Description Figure 1 shows CDS/PGA + ADC function block.
SP2 C2 CDS_in SP1 SP1 SH C1 AMP Gain setting (register) Current DAC BLKC BLKFB C3 BLKSH C4 OBP DAC Clamp data (register) ADC_in CDS AMP PG AMP 10bit ADC D0 to D9 Offset calibration logic DC offset feedback logic
VRT
Figure 1 CDS/PGA Functional Block Diagram 1. CDS (Correlated Double Sampling) Circuit The CDS circuit extracts the voltage differential between the black level and a signal including the black level. The black level is directly sampled at C1 by using the SP1 pulse, buffered by the SHAMP, then provided to the CDSAMP. The signal level is directly sampled at C2 by using the SP2 pulse, and then provided to CDSAMP (see figure 1). The difference between these two signal levels is extracted by the CDSAMP, which also operates as a programmable gain amplifier at the previous stage. The CDS input is biased with VRT (2 V). During the PBLK period, the above sampling and bias operation are paused. 2. PGA Circuit The PGAMP is the programmable gain amplifier for the latter stage. The PGAMP and the CDSAMP set the gain using 8 bits of register. The equation below shows how the gain changes when register value N is from 0 to 255. In CDSIN mode: Gain = (-2.36 dB + 0.132 dB) x N (LOG linear). In ADCIN mode: Gain = (0.57 times + 0.001784 times) x N (linear). Full-scale digital output is defined as 0 dB (one time) when 1 V is input.
Rev.1.0, Jul 06, 2004, page 6 of 28
HD49351BP/HBP 3. Automatic Offset Calibration Function and Black-Level Clamp Data Settings The DAC DC voltage added to the output of the PGA amplifier is adjusted by automatic offset calibration. The data, which cancels the output offset of the PGA amplifier and the input offset of the ADC, and the clamp data (14 LSB to 76 LSB) set by register are added and input to the DAC. The automatic offset calibration starts automatically after the RESET mode set by register is cancelled and terminates after 40,000 clock cycles (when fclk = 40.0 MHz, 1.0 ms, fclk = 20.0 MHz, 2.0 ms). 4. DC Offset Compensation Feedback Function Feedback is done to set the black signal level input during the OB period to the DC standard, and all offsets (including the CCD offset and the CDSAMP offset) are compensated for. The offset from the ADC output is calculated during the OB period, and SHAMP feedback capacitor C3 is charged by the current DAC (see figure 1). The open-loop differential gain (Gain/H) per 1 H of the feedback loop is given by the following equation. 1H is the one cycle of the OBP. Gain/H = 0.078/(fclk x C3) (fclk: ADCLK frequency, C3: SHAMP external feedback capacitor) Example: When fclk = 20 MHz and C3 = 1.0 F, Gain/H = 0.0039 DC offset compensation per 1 H (LSB) = 0.0039 x Offset error (LSB) Note: There is a maximum value in the above-mentioned amount of offset errors. When the PGAMP gain setting is changed, the high-speed lead-in operation state is entered, and the feedback loop gain is increased by a multiple of N. Loop gain multiplication factor N can be selected from 4 times, 8 times, 16 times, or 32 times by changing the register settings (see table 1). Note that the open-loop differential gain (Gain/H) must be one or lower. If it is two or more, oscillation occurs. The time from the termination of high-speed lead-in operation to the return of normal loop gain operation can be selected from 1 H, 2 H, 4 H, or 8 H. If the offset error is over 16 LSB, the high-speed lead-in operation continues, and when the offset error is 16 LSB or less, the operation returns to the normal loop-gain operation after 1 H, 2 H, 4 H, or 8 H depending on the register settings. (Refer to table 2.)
Note)
Table 1 Loop Gain Multiplication Factor during High-Speed Lead-In Operation
HGain-Nsel (register settings) [0] [1] L L H L L H H H Multiplication Factor N x4 x8 x 16 x 32
Table 2 High-Speed Lead-In Operation Cancellation Time
HGstop-Hsel (register settings) [0] [1] L L H L L H H H Cancellation Time 1H 2H 4H 8H
5. Pre-Blanking Function During the PBLK input period, the CDS input operation is separated and protected from the large input signal. The ADC digital output is fixed to clamp data (14 to 76 LSB).
Rev.1.0, Jul 06, 2004, page 7 of 28
HD49351BP/HBP 6. ADC Digital Output Control Function The ADC digital output includes the functions output enable, code conversion, and test mode. Tables 3, 4 and 5 show the output functions and the codes. Table 3 ADC Digital Output Functions
TEST0 TEST1 PBLK STBY MINV LINV
ADC Digital Output D7 D6 D5 D4
D9
D8
D3
D2
D1
D0
X X X Hi-Z X X X Hi-Z L L L Same as in table 4. L H L D9 is inverted in table 4. H L L D8 to D0 are inverted in table 4. H H L D9 to D0 are inverted in table 4. X X H Output code is set up to Clamp Level. H L L L Same as in table 5. L H L D9 is inverted in table 5. H L L D8 to D0 are inverted in table 5. H H L D9 to D0 are inverted in table 5. X X H Output code is set up to Clamp Level. H L H L H H X L L X L L H L H L H X H H L H L H L X L H L H L H H X Note: 1. STBY, TEST, LINV, and MINV are set by register. H L
X X L
X X L
Operating Mode Low-power wait state Output Hi-Z Normal operation
Pre-blanking Normal operation
L L H H
H H L L
L L H H
H H L L
L L H H
Pre-blanking Test mode
Table 4
ADC Output Code (Binary)
0 1 2 3 4 5 6 511 512 1020 1021 1022 1023
Output Pin Output Steps codes
D9 L L L L L L L
L H H H H H
D8 L L L L L L L
H L H H H H
D7 L L L L L L L
H L H H H H
D6 L L L L L L L
H L H H H H
D5 L L L L L L L
H L H H H H
D4 L L L L L L L
H L H H H H
D3 L L L L L L L
H L H H H H
D2 L L L L H H H
H L H H H H
D1 L L H H L L H
H L L L H H
D0 L H L H L H L
H L L H L H
Table 5
ADC Output Code (Gray)
0 1 2 3 4 5 6 511 512 1020 1021 1022 1023
Output Pin Output Steps codes
D9 L L L L L L L
L H H H H H
D8 L L L L L L L
H H L L L L
D7 L L L L L L L
L L L L L L
D6 L L L L L L L
L L L L L L
D5 L L L L L L L
L L L L L L
D4 L L L L L L L
L L L L L L
D3 L L L L L L L
L L L L L L
D2 L L L L H H H
L L L L L L
D1 L L H H H H L
L L H H L L
D0 L H H L L H H
L L L H H L
Rev.1.0, Jul 06, 2004, page 8 of 28
HD49351BP/HBP 7. Adjustment of Black-Level S/H Response Frequency Characteristics The CR time constant that is used for sampling/hold (S/H) at the black level can be adjusted by changing the register settings, as shown in table 6. Table 6 SHSW CR Time Constant Setting
SHSW-fsel (Register setting) [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] LLLLHLLLLHLLHHLLLLHLHLHLLHHLHHHL CR Time Constant (Typ) 2.20 nsec 2.30 nsec 2.51 nsec 2.64 nsec 2.93 nsec 3.11 nsec 3.52 nsec 3.77 nsec (cutoff frequency conversion) (72 MHz) (69 MHz) (63 MHz) (60 MHz) (54 MHz) (51 MHz) (45 MHz) (42 MHz) SHSW-fsel (Register setting) [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] [0] [1] [2] [3] LLLHHLLHLHLHHHLHLLHHHLHHLHHHHHHH CR Time Constant (Typ) 4.40 nsec 4.80 nsec 5.87 nsec 6.60 nsec 8.80 nsec 10.6 nsec 17.6 nsec 26.4 nsec (cutoff frequency conversion) (36 MHz) (33 MHz) (27 MHz) (24 MHz) (18 MHz) (15 MHz) (9 MHz) (6 MHz)
8. The SHAMP frequency characteristics can be adjusted by changing the register settings and the C4 value of the external pin. The settings are shown in table 7. Values other than those shown in the table 7 cannot be used.
BLKC 31 C
Recommendation value of C is 1000 pF
Table 7
SHAMP Frequency Characteristics Setting
[0] L [1] L [0] H SHA-fsel (Register setting) [1] [0] [1] L L H 116 MHz 75 MHz 13000 pF 10000 pF (270 pF) (300 pF) 32 MHz 49 MHz 22000 pF 15000 pF (750 pF) (620 pF) [0] H [1] H
230 MHz 6800 pF (240 pF) "Hi" 100 MHz 10000 pF (560 pF) Note: Upper line : SHAMP cutoff frequency (Typ) Middle line : Standard value of C4 (maximum value is not defined) Lower line : Minimum value of C4 (do not set below this value)
LoPwr (Register setting) "Lo"
56 MHz 18000 pF (360 pF) 24 MHz 27000 pF (820 pF)
Rev.1.0, Jul 06, 2004, page 9 of 28
HD49351BP/HBP
Timing Chart
Figure 2 shows the timing chart when CDS_in and ADC_in input modes are used.
0 1 2 ~ 9 10 11
* When CDS_in input mode is used
N N+1 N+2 N+9 N+10 N+11
CDS_in
SP1
SP2
ADCLK
D0 to D9
N-10
N-9
N-8
N-1
N
* When ADC_in input mode is used
N ADC_in N+1 N+2 N+8 N+9 N+10 N+11
ADCLK
D0 to D9
N-9
N-8
N-1
N
N+1
Figure 2 Output Timing Chart when CDS_in and ADC_in Input Modes are Used * The ADC output (D0 to D9) is output at the rising edge of the ADCLK in both modes. * Pipe-line delay is ten clock cycles when CDS_in is used and nine when ADC_in is used. * In ADC_in input mode, the input signal is sampled at the rising edge of the ADCLK.
Rev.1.0, Jul 06, 2004, page 10 of 28
HD49351BP/HBP
Detailed Timing Specifications
Detailed Timing Specifications when CDS_in Input Mode is Used Figure 3 shows the detailed timing specifications when the CDS_in input mode is used, and table 8 shows each timing specification.
Black level
CDS_in
(2) (1) (5) (4) (3)
Signal level
SP1
Vth
SP2
(7)
(6) (8) (9) (10)
Vth Vth
ADCLK
D0 to D9
Figure 3 Detailed Timing Chart when CDS_in Input Mode is Used Table 8
No. (1) (2) (3) (4) (5) (6) (7), (8) (9) (10)
Timing Specifications when the CDS_in Input Mode is Used
Timing Black-level signal fetch time SP1 `Hi' period Signal-level fetch time SP2 `Hi' period SP1 falling to SP2 falling time SP1 falling to ADCLK rising inhibit time ADCLK tWH min./tWL min ADCLK rising to digital output holding time ADCLK rising to digital output delay time Symbol tCDS1 tCDS2 tCDS3 tCDS4 tCDS5 tCDS6 tCDS7, 8 tCHLD9 tCOD10 Min -- Typ x 0.8 -- Typ x 0.8 Typ x 0.85 -- 11 -- -- Typ (1.5) 1/4fCLK (1.5) 1/4fCLK 1/2fCLK (5) -- (7) (16) Max -- Typ x 1.2 -- Typ x 1.2 Typ x 1.15 -- -- -- -- Unit ns ns ns ns ns ns ns ns ns
OBP Detailed Timing Specifications Figure 4 shows the OBP detailed timing specifications. The OB period is from the fifth to the twelfth clock cycle after the OB pulse is inputted. The average of the black signal level is taken for eight input cycles during the OB period and it becomes the clamp level (DC standard).
OB period *1
CDS_in OBP
N
N+1
N+5
N+12
N+13
OB pulse > 2 clock cycles
Note: 1. Shifts 1 clock cycle depending on the OBP input timing.
Figure 4 OBP Detailed Timing Specifications
Rev.1.0, Jul 06, 2004, page 11 of 28
HD49351BP/HBP Detailed Timing Specifications at Pre-Blanking Figure 5 shows the pre-blanking detailed timing specifications.
PBLK
Vth
VOH Digital output (D0 to D9) ADC data Clamp Level ADCLK x 10 clock ADC data VOL ADCLK x 2 clock
Figure 5 Detailed Timing Specifications at Pre-Blanking Detailed Timing Specifications when ADC_in Input Mode is Used Figure 6 shows the detailed timing chart when ADC_in input mode is used, and table 9 shows each timing specification.
ADC_in
(2) (3) (4) (5)
(1)
ADCLK
Vth
D0 to D9
VDD/2
Figure 6 Detailed Timing Chart when ADC_in Input Mode is Used Table 9
No. (1) (2), (3) (4) (5)
Timing Specifications when ADC_in Input Mode is Used
Timing Signal fetch time ADCLK tWH min./tWL min. ADCLK rising to digital output hold time ADCLK rising to digital output delay time Symbol tADC1 tADC2, 3 tAHLD4 tAOD5 Min -- Typ x 0.85 -- -- Typ (6) 1/2fADCLK (14.5) (23.5) Max -- Typ x 1.15 -- -- Unit ns ns ns ns
Rev.1.0, Jul 06, 2004, page 12 of 28
HD49351BP/HBP Dummy Clamp It adjusts the mis-clamp which occurs when taking the photo under the highlight conditions. (Like a sun) Normally it woks with the OB clamp, however when black level is out of the range caused by hightlight enter to OB part, it changes to clamp processing by dummy bit level. Resister settings are follows.
D12, D11, D10 (Dummy CP) of address H'F7 0, 0, 0 ; OFF 0, 0, 1 ; +32 0, 1, 0 ; +64 0, 1, 1 ; +96 : : 1, 1, 1 ; +224 The amount of offset are changes automatically depends on PGA gain in the LSI. D8, D9 (DMCG) of address H'F7 The amount of feed back current can be reduced with only dummy clamp. Data = 0:1/4 1:1/8 2:1/16 3:1/32
SP2 CDS_in SP1 SP1 VRT SH AMP CDS AGC ADC
Detect 8clk from OBP edge Digital output OB DET Dummy Detect 4clk DET from CPDM edge
D8 to D9 of address H'F7 Current cell BLKSH
- +
)-( )+( +
BLKFB
- + on/off Clamp level D10 to D12 of address H'F7
Note: OB/Dummy switching part has 1/8 hysteresis of threshold value.
Figure 7 Internal Bias Circuitry
Rev.1.0, Jul 06, 2004, page 13 of 28
HD49351BP/HBP
Absolute Maximum Ratings
(Ta = 25C)
Item Power supply voltage Power dissipation Operating power supply voltage Analog input voltage Digital input voltage Operating temperature Storage temperature Symbol Vdd(max) Pt(max) Vopr VIN(max) VI(max) Topr Tstg Ratings 4.1 500 2.70 to 3.45 -0.3 to AVdd +0.3 -0.3 to DVdd +0.3 -10 to +75 -55 to +125 Unit V mW V V V C C
Note: AVdd, AVss are analog power source systems of CDS, PGA, and ADC. DVdd1, DVss1 are digital power source systems of CDS, PGA and ADC. DVdd2, DVss2 are buffer power source systems of ADC output. DVdd3, DVss3 are general digital power source systems of TG. DVdd4, DVss4 are buffer power source systems of H1 and H2. * Pin 2 multi bonds the DVss1 and DVss2 * When pin 64 is set to Low, pin 41 = STROB output, pin 39 = SUB_SW output When Hi, pin 41 = Vgate input, pin 39 = ADCLK input
Electrical Characteristics
(Unless specified, Ta = 25C, AVdd = 3.0 V, DVdd = 3.0 V, and RBIAS = 33 k) * Items Common to CDS_in and ADC_in Input Modes
Item Power supply voltage range Conversion frequency Digital input voltage Symbol Vdd fCLK hi fCLK low VIH2 VIL2 Digital output voltage Digital input current Digital output current ADC resolution ADC integral linearity ADC differential linearity Sleep current VOH VOL IIH IIL IOZH IOZL RES INL DNL ISLP Min 2.70 20 5.5
2.25 x DVdd 3.0
Typ 3.00 -- -- -- -- -- -- -- -- -- -- 10 (2) (0.3) 0
Max 3.45 36 25 DVdd
0.6 x DVdd 3.0
Unit V MHz MHz V V V V A A A A bit LSBp-p LSB A
Test Conditions
Remarks
LoPwr = low *1 LoPwr = high
HD49351HBP HD49351BP All of digital input pin
0 DVdd -0.5 -- -- -50 -- -50 -- -- -- -100
-- 0.5 50 -- 50 -- -- -- -- 100
IOH = -1 mA IOL = +1 mA DVdd = VIH = 3.0 V VIL = 0 V VOH = Vdd VOL = 0 V fCLK = 20 MHz fCLK = 20 MHz Fix digital input pin to 0 V, output pin should open Fix digital I/O pin to 0V
RL = 2 k, CL = 10 pF
*2
Standby current Digital output Hi-Z delay time
ISTBY tHZ tLZ tZH tZL
-- -- -- -- --
3 -- -- -- --
5 100 100 100 100
mA ns ns ns ns
Refer to figure 7
Notes: 1. It is expressing on the frequency in an analog circuit part. Please keep in your mind that TG part has 2 divided, 3 divided mode. 2. Differential linearity is the calculated difference in linearity errors between adjacent codes. 3. Values within parentheses ( ) are for reference.
Rev.1.0, Jul 06, 2004, page 14 of 28
HD49351BP/HBP
Electrical Characteristics (cont.)
(Unless specified, Ta = 25C, AVdd = 3.0 V, DVdd = 3.0 V, and RBIAS = 33 k) * Items for CDS_in Input Mode
Item Consumption current (1) Consumption current (2) CCD offset tolerance range Timing specifications (1) Timing specifications (2) Timing specifications (3) Timing specifications (4) Timing specifications (5) Timing specifications (6) Timing specifications (7) Timing specifications (8) Timing specifications (9) Timing specifications (10) Clamp level Symbol IDD1 IDD2 VCCD tCDS1 tCDS2 tCDS3 tCDS4 tCDS5 tCDS6 tCDS7 tCDS8 tCHLD9 tCOD10 CLP(00) CLP(09) CLP(31) PGA gain at CDS input PGA(0) PGA(63) PGA(127) PGA(191) PGA(255) Min -- -- (-150) -- Typ x 0.8 -- Typ x 0.8 Typ x 0.85 -- 11 11 -- -- -- -- -- -4.4 4.1 12.5 21.0 29.4 Typ (65) (50) -- (1.5) 1/4fCLK (1.5) 1/4fCLK 1/2fCLK (5) -- -- (7) (16) (14) (32) (76) -2.4 6.1 14.5 23.0 31.4 Max -- -- (150) -- Typ x 1.2 -- Typ x 1.2 Typ x 1.15 -- -- -- -- -- -- -- -- -0.4 8.1 16.5 25.0 33.4 Unit mA mA mV ns ns ns ns ns ns ns ns ns ns LSB LSB LSB dB dB dB dB dB CL = 10 pF CL = 10 pF Refer to table 8 Test Conditions fCLK = 36 MHz fCLK = 20 MHz Remarks CDS_in mode LoPwr = low CDS_in mode LoPwr = high
Note: Values within parentheses ( ) are for reference.
* Items for ADC_in Input Mode
Item Consumption current (3) Consumption current (4) Timing specifications (11) Timing specifications (12) Timing specifications (13) Timing specifications (14) Timing specifications (15) Input current at ADC input Clamp level at ADC input PGA gain at ADC input Symbol IDD3 IDD4 tADC1 tADC2 tADC3 tAHLD4 tAOD5 IINCIN OF2 GSL(0) GSL(63) GSL(127) GSL(191) GSL(255) Min -- -- -- Typ x 0.85 Typ x 0.85 -- -- -110 462 0.45 1.36 2.27 3.18 4.08 Typ (35) (20) (6) 1/2fADCLK 1/2fADCLK (14.5) (23.5) -- 512 0.57 1.71 2.86 4.00 5.14 Max -- -- -- Typ x 1.15 Typ x 1.15 -- -- 110 562 0.72 2.16 3.60 5.04 6.47 Unit mA mA ns ns ns ns ns A LSB Times Times Times Times Times CL = 10 pF CL = 10 pF VIN = 1.0 to 2.0 V Test Conditions fCLK = 36 MHz fCLK = 25 MHz Remarks ADC_in mode LoPwr = low ADC_in mode LoPwr = high Refer to table 9
Note : Values within parentheses ( ) are for reference.
Rev.1.0, Jul 06, 2004, page 15 of 28
HD49351BP/HBP Serial Interface Specifications Timing Specifications
Data is determined at CS rising edge tINT2
tINT1 CS SCK tsu SDATA tho Latches SDATA at SCK rising edge fSCK
D8 D9 D10 D11 D12 D13 D14 D15 D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7
STD2(Upper data)
STD1(Lower data)
address(address)
Figure 8 Serial Interface Timing Specifications
Item fSCK tINT1,2 tsu tho Min -- 50 ns 50 ns 50 ns Max 5 MHz -- -- -- Notes: 1. 2. 3. 4. 5. 3 byte continuous communications. Input SCK with 24 clock when CS is Low. It becomes invalid when data communications are stopped on the way. Data becomes a default with hardware reset. Input more than double frequency of SCK to the CLK_in when transfer the serial data.
The Kind of Data Data address has 256 type. H'00 to H'FF
H'00 : : H'EF H'F0 : : H'FF
Data at timing generator part
Data at CDS part
Address map of each data referred to other sheet. Details of timing generator refer to the timing chart on the other sheet together with this specification. This specification only explains about the data of CDS part.
Rev.1.0, Jul 06, 2004, page 16 of 28
HD49351BP/HBP Explanation of Serial Data of CDS Part Serial data of CDS part are assigned to address H'F0 to H'F8. Functions are follows.
1
1
1
Address 1 0
0
0
0
STD1[7:0] (L) STD2[15:8] (H) D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 PGA gain test_I1
* PGA gain (D0 to D7 of address H'F0) Details are referred to page 6 block diagram. At CDS_in mode: -2.36 dB + 0.132 dB x N (Log linear) At ADC_in mode: 0.57 times + 0.01784 times x N (Times linear) : Full-scale digital output is defined as 0 dB when 1 V is input. Above PGA gain definition means input signal 1 Vp-p to CDS_in, and set N = 18 (correspond 2.36 dB), and then PGA outputs the 2 V full-range, and also ADC outputs the full code (1023). This mean offset gain of PGA has 6 dB - 2.36 dB = 3.64 dB, therefore it should be decided that how much dB add on.
(1.0 V) (2.0 V) (1023)
(1.0 V) CDS PGA ADC
0 dB when set N = 18 which correspond to 2.36 dB (1) Level dia explain 2V 1023
CDS
PGA
ADC
(CDS = 0 dB) 3.64 dB + 0.132 dB x N (2) Level dia on the circuit
Figure 9 Level Dia of PGA * Test_I1 (D13 to D15 of address H'F0) It controls the standard current of analog amplifier systems of CDS, PGA. Use data = 4 (D15 = 1) normally. When data = 0, 50% current value with default When data = 4, default When data = 7, 150% current value with default
1
1
1
Address 1 0
0
0
1
STD1[7:0] (L) STD2[15:8] (H) D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8
STBY MINV LINV test0 SLP
test_I2
SHSW_fsel
SHA_fsel
* SLP and STBY (D0, D1 of address H'F1) SLP: Stop the all circuit. Consumption current of CDS part is less than 10 A. Start up from offset calibration when recover is needed. STBY: Only the standard voltage generating circuit is operated. Consumption current of CDS part is about 3 mA. Allow 50 H time for feedback clamp is stabilized until recover.
Rev.1.0, Jul 06, 2004, page 17 of 28
HD49351BP/HBP * Output mode (D2 to D4 of address H'F1 and address H'F4 of D6) It is a test mode. Combination details are page 8. Normally set to all 0. * SHA-fsel (D8 to D9 of address H'F1) It is a LPF switching of SH amplifier. Frequency characteristics are referred to page 9. To get rough idea, set the double cut off frequency point with using. * SHSW-fsel (D10 to D13 of address H'F1) It is a time constant which sampling the black level of SH amplifier. Frequency characteristics are referred to page 9. To get rough idea, set the double cut off frequency point with using. S/N changes by this data, so find the appropriate point with set data to up/down. * Test_I2 (D14 to D15 of address H'F1) Current of ADC analog part can be set minutely. Normally use data = 0. 0: Default (100%) 1: 150% 2: 50% 3: 80%
1
1
1
Address 1 0
0
1
0
STD1[7:0] (L) D4 D3 D2
D1
STD2[15:8] (H) D0 D15 D14 D13 D12 D11 D10 D9
D8
CDS_buff
Low_pwr
Reset
AD_sel
Clamp level
HGain-Nsel HGstop-Hsel
* Clamp (D0 to D4 of address H'F2) Determine the OB part level with digital code of ADC output. Clamp level = setting data x 2 + 14 Default data is 9 = 32 LSB. * HGstop-Hsel, HGain-Nsel (D8 to D11 of address H'F2) Determine the lead-in speed of OB clamp. Details are referred to page 7. PGA gain need to be changed for switch the high speed leading mode. Transfer the gain +1/-1 to previous field, its switch to high speed leading mode. * Low_PWR (D12 of address H'F2) Switch circuit current and frequency characteristic. Data = 0: 40 MHz guarantee Data = 1: 25 MHz guarantee * ADSEL (D14 of address H'F2) Data = 0: Select CDS_in Data = 1: Select ADC_in * Reset (D15 of address H'F2) Software reset. Data = 1: Normal Data = 0: Reset Offset calibration should be done when starting up with using this bit. Details are referred to page 23.
Address 1 0 STD1[7:0] (L) STD2[15:8] (H) D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8
1
1
1
0
1
1
* Address H'F3 are all testing data. Normally set to all 0., or do not transfer the data.
Rev.1.0, Jul 06, 2004, page 18 of 28
HD49351BP/HBP
Address 1 0 STD1[7:0] (L) D7 D6 D5 D4 D3 D2 D1 D0 VD latch H12_Buff MON STD2[15:8] (H) D12 D11 D10 D9 D8 Gray_test Gray code
1
1
1
1
0
0
* MON (D0 to D2 of address H'F4) Select the pulse which output to pin MON (pin 60). When D0 to D2: 0, Fix to Low When 1, ADCLK When 2, SP1 When 3, SP2 When 4, OBP When 5, PBLK When 6, CPDM When 7, DLL_test * H12Baff (D3 to D6 of address H'F4) Select the buffer size which output to pin H1A, H2A (pin 22, 26). D3: 2 mA buffer D4: 4 mA buffer D5: 10 mA buffer D6: 14 mA buffer Above data can be on/off individually. Default is D6 can be on only. (18 mA buffer) * VD latch (D7 of address H'F4) Data = 0: Gain data is determined when CS rising Data = 1: Gain data is determined when VD rising * Gray (D8 to D9 of address H'F4) ADC output code can be change to following types. Differential code is mentioned to next page.
Gray Code [1] 0 0 1 1 Gray Code [0] 0 1 0 1 Output Code Binary code Gray code Differential encoded binary Differential encoded gray
* Gray_test (D10 to D12 of address H'F4) Data which determine the differential code and standard phase of gray code.
Rev.1.0, Jul 06, 2004, page 19 of 28
HD49351BP/HBP * Gray code (D8 to D12 of address H'F4) ADC output code can be change to following type by differential code gray SW (D9, D8). Binary code at D8: 0, Gray code at D8: 1 Normal at D9: 0, differential code at D9: 1 Differential code and gray code are recommended for this countermeasure. Figure 10 indicates circuit block. When luminance signal changes are smoothly, the number of bit of switching digital output bit can be reduced and easily to reduce the ripple using this function. This function is especially effective for longer the settings of sensor more than clk = 30 MHz, and ADC output. Figure 12 indicates the timing specifications.
Standard Phase (D10) 0 1 0 1 Standard Phase (D11) 0 0 1 1 Standard Data Output timing at Selecting the Differential Code Third and fourth Fourth and fifth Fifth and sixth Sixth and seventh
* adck phase (D12): ADCK polar to OBP When 0: Select positive edge When 1: Select negative edge
Note: Color filter is different1 in the number of pixels with odd number and even number therefore first 2 pixcels should be standard.
10 ADC
Differential SW(D9) + - Carry bit rounding Standard data selector
Gray SW(D8)
10 Output
2clk_DL Standard data control signal (D10, D11)
Convert GrayBinary
Figure 10 Differential Code and Gray Code Circuit
(In case of select the positive edge of ADCLK with D12)
ADCLK OBP (In case of select the positive polar) Digital output Differential data
(Beginning edge of OBP and standard edge of ADCLK should be exept 5 ns) 1 2 3 4 5 6 7 8
Standard data
Differential data
Figure 11 Timing Specification of Differential Code
Carry bit rounding Standard data selector 2clk delay D11 D10 D9 D11 D10 D9
From ADC
Convert GrayBinary
Standard data control signal
D0
D0
(1) Complex differential coded
(2) Convert Gray Binary
Figure 12 Complex Circuit Example at the DSP Side
Rev.1.0, Jul 06, 2004, page 20 of 28
HD49351BP/HBP
Address 1 0 STD1[7:0] (L) D7 D6 D5 D4 D3 D2 D1 D0 P_RG Address 1 1 P_ADCLK P_SP2 P_SP1 STD2[15:8] (H) D12 D11 D10 D9 D8 DLL current DLL steps
1
1
1
1
0
1
1
1
1
0
0
0
D6
STD1[7:0] (L) D5 D4 D2 P_SP2
D1
STD2[15:8] (H) D0 D15 D14 D13 D12 D10 D9 D8 P_RG P_ADCLK
P_SP1 2,3 divided select
* Address H'F5 sets the DLL delay time and selects the 1/4 phase. Details are on the next page. And D15 of address H'F8 can switch 2/3 divided mode but ensure that this address data relative to valid/invalid.
D15 of address H'F8 = 0 Divided mode D0 to D7 of address H'F5 D0 to D14 of address H'F8 Select the 2 divided, 1/4 phase Valid Invalid D15 of address H'F8 = 1 Select the 3 divided, 1/6 phase Invalid Valid
* Phase settings of high speed pulse (address H'F5 to H'F8) (1) Select the 1/4 phase from figure 13 at 2 divided mode (D15 = 0 of address H'F8). Select the 1/6 phase from figure 14 at 3 divided mode (D15 = 1 of address H'F8). *****P_SP1, P_SP2, P_ADCLK, P_RG (2) Then select the necessary delay time from figure 15. *****DL_SP1, DL_SP2, DL_RG, DL_ADCLK RG can be set both of rising / falling edge optionally.
H1 Data = 0 P_SP1 P_SP2 Data = 1 Data = 2 Data = 3 P_ADCLK P_RG H1 Data = 0 Data = 1 Data = 2 Data = 3
Figure 13 2 Divided Mode, 1/4 Phase Select (Valid at D15 = 0 of address H'F8)
H1 Data = 5 Data = 0 P_SP1 P_SP2 Data = 1 Data = 2 Data = 3 Data = 4 P_ADCLK P_RG H1 Data = 0 Data = 1 Data = 2 Data = 3 Data = 4 Data = 5
Figure 14 3 Divided Mode, 1/6 Phase Select (Valid at D15 = 1 of address H'F8) Default Value of Each Phases
P_SP1 2 divided mode 3 divided mode 1 0 P_SP2 2 3 P_ADCLK 1 1 P_RG 0 5
Note: 50% of duty pulse makes tr, tf of RG by DLL.
Rev.1.0, Jul 06, 2004, page 21 of 28
HD49351BP/HBP
Address 1 0 STD1[7:0] (L) D7 D6 D5 D4 D3 D2 D1 D0 DL_SP2 Address 1 0 DL_SP1 STD2[15:8] (H) D12 D11 D10 D9 D8 CDS_test DL_ADCLK
1
1
1
1
1
0
1
1
1
1
1
1
STD1[7:0] (L) D7 D6 D5 D4 D3 D2 D1 D0 DL_RG_f DL_RG_r
STD2[15:8] (H) D12 D11 D10 D9 D8 Dummy clamp th Dummy clamp current
(3) Setting method of DLL
1. DLL step decides the how many divide the 1 cycle of sensor CLK. For reference, set 1 ns(when 2 ns DLL_current bit = 0, ADCLK(0) when 1 set to 1 ns) (In phase with H1) Can be set 16 to 64 steps by 4 steps. Steps = 4 + (4 x N); possible to set N = 3 to 15 Recommended steps is clk_in = when 11 to 14 MHz: H'0E(60 steps) when 14 to 22MHz: H'09(40 steps) when 22 to 50MHz: H'1E(60 steps) P_ADCLK when 50 to 72MHz: H'19(40 steps) 2. Can be change each 4 type of pulse 0 to 15 steps with 1 step. (1 ns or 2 ns divide) 3. Select the 2 ns divide when sensor CLK is less than 15 MHz. P_SP1 H1 DL_RG DL_SP1 DL_SP2 DL_ADCLK 0 14 42 28 Default 56
(Rising)
Control voltage
DLL_C
DLL = 64 steps
PC
DLL = 15 steps
DL_ADCLK DLL = 15 steps
DL_SP1 P_SP2 DLL = 15 steps
10
DL_SP2 ADCLK (0, 0) DLL = 15 steps
(Falling) AND
DL_RG
Figure 15 Analog Delay (DLL) Circuit Block. * CDS_test (D12 of address H'F6) It is testing data. Normally set to 0. * Dummy clamp current (D9 to 8 of address H'F7) Data = When 0, 1/4 When 1, 1/8 When 2, 1/16 When 3, 1/32 Details are refer to page 13. * Dummy clamp threshold (D12 to 10 of address H'F7) Data = When 0, off When 1, When 2, +64 When 3, When 4, +128 When 5, When 6, +192 When 7, Details are refer to page 13.
+32 +96 +160 +224
Rev.1.0, Jul 06, 2004, page 22 of 28
HD49351BP/HBP
Operation Sequence at Power On
Must be stable within the operating power supply voltage range VDD
CLK_in 3clk or more Hardware Reset 6clk or more HD49351 serial data transfer (1) (2) (3) SP1 Start control SP2 ADCLK of TG and camera DSP OBP etc. Note: At 2 divided mode: ADCLK = 1/2CLK_in At 3 divided mode: ADCLK = 1/3CLK_in 2ms or more (Charge of external C) 40,000ADCLK or more (offset calibration)
(4)
(5)
RESET bit
CDS_Reset = Low
Automatic offset calibration
Automatic adjustment taking 40,000ADCLK period after Reset cancellation
The following describes the above serial data transfer. For details of resistor settings are referred to serial data function table. : Wait more than 6clk after release the hardware Reset and then transfer the necessary data to TG part. (2) DLL data transfer of CDS part : Transfer the phase data of RG, SP1, SP2, ADCLK of CDS part. (3) Reset=L of CDS part : Transfer Reset bit = 0 of address H'F2. (4) Reset=H of CDS part : Transfer Reset bit = 1 of address H'F2. (Reset release) (5) Other data of CDS part : Transfer the SH_SW_fsel and other PGA. Before transfer the Reset bit = 0, TG series pulse need to be settled, so address H'00 to H'EF of TG part and H'F4 to H7F7 of CDS part should transfer in advance. (1) Resistor transfer of TG part
Figure 16 Operation Sequence at Power On
Rev.1.0, Jul 06, 2004, page 23 of 28
HD49351BP/HBP
Timing Specifications of High Speed Pulse
* H1, H2, RG waveform
tr twh tf
H2
90% 50% 10%
H1
two tr 90% 50% 10% twh tf twl tH1DL
RG
twl
twh Item H1/H2 RG XV1 to 4 CH1 to 4 XSUB/SUB_SW min 14 7 -- -- -- typ 20 10 -- -- -- max -- -- -- -- -- min 14 -- -- -- --
twl typ 20 37 -- -- -- max -- -- -- -- -- min -- -- -- -- --
tr typ 8.0 4.0 20 20 20 max 14 -- -- -- -- min -- -- -- -- --
tf typ 8.0 4.0 20 20 20 max 14 -- -- -- --
Load Unit capacitance ns ns ns ns ns 165 pF 15 pF 15 pF 15 pF 15 pF
two Item H1/H2 overlap min 12 typ 20 max -- Unit ns
Power supply specification of H1, H2, RG are 3.0 V to 3.3 V. Values are sensor CLK = when 18 MHz.
Rev.1.0, Jul 06, 2004, page 24 of 28
HD49351BP/HBP
Notice for Use
1. Careful handling is necessary to prevent damage due to static electricity. 2. This product has been developed for consumer applications, and should not be used in non-consumer applications. 3. As this IC is sensitive to power line noise, the ground impedance should be kept as small as possible. Also, to prevent latchup, a ceramic capacitor of 0.1 F or more and an electrolytic capacitor of 10 F or more should be inserted between the ground and power supply. 4. Common connection of AVDD and DVDD should be made off-chip. If AVDD and DVDD are isolated by a noise filter, the phase difference should be 0.3 V or less at power-on and 0.1 V or less during operation. 5. If a noise filter is necessary, make a common connection after passage through the filter, as shown in the figure below.
Analog +3.0V AVDD AVSS Noise filter DVDD1 to 4 HD49351 DVSS DVSS Digital +3.0V Noise filter AVDD AVSS 0.01 F Example of noise filter 100 H 0.01 F
DVDD1 to 4 HD49351
6. Connect AVSS and DVSS off-chip using a common ground. If there are separate analog system and digital system set grounds, connect to the analog system. 7. When VDD is specified in the data sheet, this indicates AVDD and DVDD. 8. No Connection (NC) pins are not connected inside the IC, but it is recommended that they be connected to power supply or ground pins or left open to prevent crosstalk in adjacent analog pins. 9. To ensure low thermal resistance of the package, a Cu-type lead material is used. As this material is less tolerant of bending than Fe-type lead material, careful handling is necessary. 10. The infrared reflow soldering method should be used to mount the chip. Note that general heating methods such as solder dipping cannot be used. 11. Serial communication should not be performed during the effective video period, since this will result in degraded picture quality. Also, use of dedicated ports is recommended for the SCK and SDATA signals used in the HD49330AF. If ports are to be shared with another IC, picture quality should first be thoroughly checked. 12. At power-on, automatic adjustment of the offset voltage generated from PGA, ADC, etc., must be implemented in accordance with the power-on operating sequence (see page 23). 13. Ripple noise of DC/DC converter which generates the voltage of analog part should set under -50 dB with power supply voltage.
Rev.1.0, Jul 06, 2004, page 25 of 28
HD49351BP/HBP
Example of Recommended External Circuit
Pin 57
* Slave mode Pin 57(Test1 = Low) to CCD 47 3.0V 47 47/6 + 0.1
Mode Slave mode Master mode
Specification CLK, HD, VD input from SSG. HD, VD output
Low Hi
Pin 56 = Low: TESTIN mode. Please do not use. Reset(Normally Hi) 0.1
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
XV3
33 XV4 to V.Baff 34 CH1 35 CH2 36 CH3 37 CH4 38 XSUB to CCD
XV2 XV1 DVDD3 DVDD4 1/4clk_o H2A DVSS4 DVSS4 1/2clk_o H1A DVDD4 DVDD3 RG Reset
VD_in
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
from Pulse generator
39 SUB_SW/ADCK_in 40 SUB_PD 41 STROB/Vgate 42 DVSS3 43 AVSS 44 ADC_in 33k 0.1 0.1 0.1 45 BIAS 46 VRB 47 VRT 48 VRM HD49351
BLKC CDS_in AVDD BLKFB BLKSH AVSS Test2 Test1 DLL_C DVDD1 MON 41pin_cont CS Sdata
HD_in CLK_in DVSS3 DVDD2 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DVSS1,2 ID SCK
to Camera signal processor
ID pulse
AVDD
47 0.1 + 47/6
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 1 100p Serial data input 0.1
47/6
Pin 61 = Low: Pin 41 is STROB output Pin 39 is SUB_SW output Pin 61 = Hi: Pin 41 is Vgate output Pin 39 is Hiz
CCD signal input * Master mode Pin 57(Test1 = Hi)
1000p
to CCD 47 3.0V 47 47/6 + 0.1 Reset(Normally Hi) 0.1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 to Camera signal processor from Pulse generator
XV3
33 XV4 to V.Baff 34 CH1 35 CH2 36 CH3 37 CH4 38 XSUB to CCD
XV2 XV1 DVDD3 DVDD4 1/4clk_o H2A DVSS4 DVSS4 1/2clk_o H1A DVDD4 DVDD3 RG Reset
VD_in
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
39 SUB_SW/ADCK_in 40 SUB_PD 41 STROB/Vgate 42 DVSS3 43 AVSS 44 ADC_in 33k 0.1 0.1 0.1 45 BIAS 46 VRB 47 VRT 48 VRM HD49351
BLKC CDS_in AVDD BLKFB BLKSH AVSS Test2 Test1 DLL_C DVDD1 MON 41pin_cont CS Sdata
HD_in CLK_in DVSS3 DVDD2 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DVSS1,2 ID SCK
+
to Camera signal processor
ID pulse
AVDD
47 0.1 + 47/6
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 1 100p Serial data input 0.1
Pin 61 = Low: Pin 41 is STROB output Pin 39 is SUB_SW output Pin 61 = Hi: Pin 41 is Vgate output 47/6 Pin 39 is Hiz Unit: R: C: F
CCD signal input
1000p
Rev.1.0, Jul 06, 2004, page 26 of 28
+
HD49351BP/HBP
* CDS single operating mode Pin 56(Test2 = Low) Pin 57 is "Don't care" in this mode. 47 3.0V 47 47/6 + 0.1 Reset(Normally Hi) 0.1 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
DVDD3 DVDD4
DVSS4 DVSS4
33 34 35 36 PBLK 37 OBP 38 CP_DM 39 ADCK 40 SP2 41 SP1 42 DVSS3 ADC_in 33k 0.1 0.1 0.1 43 AVSS 44 ADC_in 45 BIAS 46 VRB 47 VRT 48 VRM
DVDD4 DVDD3
Reset
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 to Camera signal processor
HD49351
AVDD
47 0.1 + 47/6
BLKC CDS_in AVDD BLKFB BLKSH AVSS Test2 Test1 DLL_C DVDD1 MON 41pin_cont CS Sdata
DVSS3 DVDD2 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DVSS1,2 SCK
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 1 100p Serial data input 0.1
+
Pin changes are not effective with pin 61.
47/6 Unit: R: C: F
CCD signal input
1000p
Serial data when CDS single operation mode are following resister specifications.
(Latch timing specification is same as normal mode)
CS tINT1 SCK tsu SDATA
fsck tINT2 tho D00 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15
Resister 0 D00 D01 D02 D03 D04 Low Low Low X X 0 0 0
Resister 1 High Low Low 1 0 0
Resister 2 Low High Low 0 1 0 1 0 0 1 0
Resister 3 High High Low 1 1 0
Resister 4 Low Low High 0 0 1
Resister 5 High Low High 1 0 1
Resister 6 Low High High 0 1 1
Resister 7 High High High 1 1 1 0 0 0 0 0 1 0 1 0 0
0 SLP Low: Normal 0 Clamp(0) High: Sleep 0 STBY Low: Normal 0 Clamp(1) High: Standby 0 Output mode(LINV) 0 Clamp(2) 0 Output mode(MINV) 0 Clamp(3) 0 Output mode(Test0) 0 Clamp(4) 0 SHA-fsel(0) 0 SHA-fsel(1) 0 SHSW-fsel(0) 0 SHSW-fsel(1) 0 SHSW-fsel(2) 0 SHSW-fsel(3) 0 Test_I2 (0) 1 Test_I2 (1)
0 MON(0) 0 MON(1) 0 MON(2) 0 H12Baff(0) 0 H12Baff(1) 0 H12Baff(2) test 0 H12Baff(3) 0 VD latch 0 Gray1 0 Gray2 0 Gray_ts(0) 0 Gray_ts(1) 0 Gray_ts(2)
0 P_SP1(0) 0 P_SP1(1) 0 P_SP2(0) 0 P_SP2(1) 0 P_ADCLK(0) 0 P_ADCLK(1) 1 P_RG(0) 0 P_RG(1) 0 DLL_CK(0) 0 DLL_CK(1) 0 DLL_CK(2) 0 DLL_CK(3) 0 DLL_current
1 DL_SP1(0) 0 DL_SP1(1) 1 DL_SP1(2) 1 DL_SP1(3) 1 DL_SP2(0) 0 DL_SP2(1) 0 DL_SP2(2) 0 DL_SP2(3)
0 DL_RG_r(0) 0 DL_RG_r(1) 0 DL_RG_r(2) 0 DL_RG_r(3) 0 DL_RG_f(0) 0 DL_RG_f(1) 0 DL_RG_f(2) 0 DL_RG_f(3)
D05 PGA(0) LSB D06 PGA(1) D07 PGA(2) D08 PGA(3) D09 PGA(4) D10 PGA(5) D11 PGA(6) D12 PGA(7) MSB D13 Test_I1 (0) D14 Test_I1 (1) D15 Test_I1 (2)
0 HGstop-Hsel(0) 0 0 HGstop-Hsel(1) 0 0 HGain-Nsel(0) 0 0 HGain-Nsel(1) 0 0 LoPwr Low: Normal 1 High: Low power 0 0 X 0 ADSEL Low:CDSin 0 High:ADin 0 Reset Low: Reset 1 High: Normal
1 DL_ADCLK(0) 0 DMCG(0) 0 DL_ADCLK(1) 0 DMCG(1)
1 DL_ADCLK(2) 0 Dummy CP(0) 0 1 DL_ADCLK(3) 0 Dummy CP(1) 0 1 CDS_test 0 Dummy CP(2) 0
Rev.1.0, Jul 06, 2004, page 27 of 28
HD49351BP/HBP
Package Dimensions
Unit: mm
0.20 S B
0.75
0.20 S A
6.00
0.50 x 9 = 4.50 0.50
A area
0.15
0.75
10 9 8 7 6 5 4 3 2 1 A
Index Pin
0.20 S
S
65 - 0.30 0.05 0.05 M S A B
0.25 0.05 1.20 Max
0.08 S
Details of the part A
Package Code JEDEC JEITA Mass (reference value)
TFBGA0606-65 -- -- 0.056 g
Rev.1.0, Jul 06, 2004, page 28 of 28
0.50
x4
K J H BG F E D C B A
0.50 x 9 = 4.50
6.00
Sales Strategic Planning Div.
Keep safety first in your circuit designs!
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1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein.
RENESAS SALES OFFICES
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http://www.renesas.com
(c) 2004. Renesas Technology Corp., All rights reserved. Printed in Japan.
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